1. Field of the Invention
The present invention relates to a method of forming a storage node of a Capacitor.
2. Description of the Background Art
With the development of fabrication techniques for a semiconductor device, and the extension of the applicable fields thereof, mass storage devices are being developed. In addition, with the high integration of a circuit, the area of a unit memory cell is being decreased, and cell capacitance is also being decreased. In particular, in a DRAM(Dynamic Random Access Memory), using a capacitor as an information storage unit and including a switching transistor as a controllable signal transfer unit connected to the capacitor, since a decrease in cell capacitance according to the decrease in unit memory cell area degrades the readability of a memory cell and increases soft error rate, the problem of the increase in cell capacitance must be solved for high integration of a semiconductor memory device.
The basic structure for the capacitor in the memory cell includes a lower electrode, dielectric film, and an upper electrode, and as a method for obtaining a larger capacitance in a small area, the following studies are being made.
First, the thickness of a dielectric film is closely connected with dielectric properties, and the main factors for limiting thickness are a leakage current and breakdown voltage of a dielectric. With a given thickness of the dielectric film, as the leakage current becomes smaller and the breakdown voltage becomes larger, the dielectric becomes better.
Second, in order to increase the effective area of the capacitor, various types of capacitors, such as a planar-type, trench-type, stack-type, cylinder type-type, combination thereof, etc., are formed.
Third, a high dielectric having a smaller leakage current, larger breakdown voltage, and larger dielectric constant can make the thickness of a dielectric film smaller than the physical thickness thereof, and can decrease the size of a memory cell and increase capacitance.
Among a variety of methods for increasing the effective area of a capacitor, the method for increasing capacitance by increasing the surface area of a capacitor by growing hemispherical grains (hereinafter, HSG) on the surface of a storage node, generally, a lower electrode, in a DRAM device of 16xcx9c256 MB is more frequently applied than other methods for increasing the surface area of a capacitor by forming a capacitor structure in a three-dimensional structure, such as a trench-type, cylinder-type, etc. The above method for increasing capacitance by growing HSG on the surface of a storage node is a method using an unique physical phenomenon, which occurs in a process of phase-changing amorphous silicon into polycrystal silicon. When heat is applied to amorphous silicon after depositing the amorphous silicon on the surface of a storage node, the amorphous silicon forms fine hemispherical grains to thus be changed into polycrystal silicon having an uneven surface. The surface of the storage node of the thusly-formed HSG polycrystal silicon capacitor has a surface area 2-3 times larger than a conventional smooth surface capacitor.
After the HSG growth, however, a bridge between storage nodes of the capacitor occurs due to additional growth of HSG or breakdown of HSG by thermal treatment in the successive process, thus decreasing product yield. FIG. 1A is a cross-sectional view illustrating a DRAM cell having HSG grown on inner walls and outer walls of a cup-type storage node. Reference numeral 1 denotes a gate, 2 denotes a landing pad, 3 denotes a bit line, 4 denotes a storage node contact, 5 denotes a nitride film, 6 denotes a storage node, and 7 denotes HSG, respectively. It is shown that the HSG grown on the inner and outer walls of two adjacent storage nodes are connected with one another; thereby forming a HSG bridge.
To suppress the formation of such a HSG bridge, HSG can be grown only on the inner walls of the storage node. FIG. 1B is a cross-sectional view illustrating a DRAM cell having grown HSG only on the inner walls of the cup-type storage node, wherein it is shown that HSG 7 are separated from one another by a nitride film 9. In this case, however, since the HSG.7 are grown only on the inner walls of the storage node 6, capacitance is decreased as compared to the case of growing the HSG 7 on both inner and outer walls of the storage node 6 as in FIG. 1A.
Accordingly, it is an object of the present invention to provide a method of forming a storage node of a capacitor that prevents HSG bridging while improving capacitance by growing HSG on inner and outer walls of the storage node of the capacitor.
To achieve the above object, there is provided a method of preventing HSG bridging using a nitride-spacer according to the present invention, which includes the steps of: forming a storage node of a capacitor, comprising: forming an first insulation film over a substrate; forming a trench in the first insulation film to expose an electrical contact structure; forming a second insulation film along sidewalls of the trench; forming an amorphous silicon film in the trench; removing the second insulation film so that sidewalls of the amorphous silicon film are separated from sidewalls of the trench; and growing HSG on exposed surfaces of the amorphous silicon film.
To form the second insulation film, dry etching is carried out. The second insulation film is made to have a thickness of 200xcx9c500 xc3x85. Also, the amorphous silicon film is planarized using a planarization film, e.g., SOG (silicon oxide glass) or PSG (phosphosilicate glass).
By this method, the first insulation film serves as a barrier between storage nodes, and the second insulation film provides a space for growing HSG on the outer walls of the storage node, thus growing HSG on both inner and outer walls of the storage node without bridging.